MaxiMem - An EU SME-2 Horizon 2020 Funded Project

What is MaxiMem?

Overview

MaxiMem is an innovative, patented compression/decompresison technology that consists of a silicon memory compression IP block on a SoC (System on a Chip). It exploits the memory resources of computing devices so effectively that it doubles memory capacity and bandwidth and potentially speed and performance, potentially cutting current energy consumption in half.

Our technology is high-performance, transparent to application software and is data lossless. It compresses the data effectively and ultra-fast through novel implementation strategies in hardware.

 

Overcoming barriers to innovation in the semiconductor industry

Before licensing an IP block, customers need to know how well it will work for a specific application in their particular architecture. This generally means implementing it in a demo chip at high upfront cost. This is a key technological and cost barrier to innovation in this industry.

To mitigate this risk, and turn it into an opportunity, we will create a suite of tools that allow for detailed parameter testing under different simulated conditions. These tools will show the benefits of our solution in a specific customer’s system. In combination with the parallel development of a demonstrator SoC, funded through other European sources (EuroEXA), the tools developed in the current SME-2 project will ensure our success in the market.

 

MaxiMem and Ziptilion™

When the application for this project was filed the product name was MaxiMem. During the course of the project it so turned out that it was not possible to protect the MaxiMem brand in the targeted markets, therefore the product has changed name from MaxiMem to Ziptilion™.

 

Work plan

The project includes six work packages (WP) organised around the following activity sets:

  1. Development: WP 1-3 develop a set of tools with which the customer will be able to validate for themselves the expected performance of Ziptilion™ in their processor subsystem.
  2. User testing: In WP4 the prospective customer will use our tools to validate the expected perfomance, possibly in iterations where minor adjustments are done on the tools to maximally demonstrate the potential of Ziptilion™ for the customer. In this WP we will also assess the technical results from the customer testing.
  3. Business: To ensure we are ready for market expploitation once the current project is complete. WP5 includes business development activities and customer recruitment while WP6 is for project management.

Dissemination and Achievements

These activities have been accomplished.

 

2019

2020

Communication Plan

The planned commuication and information activities is presented here. Also the development of Ziptilion™ and communication of the activities and results are going to be listed here.

 

2020

2021

The Ziptilion™ Technology​

The Challenge

Technology continues to grow in complexity and computer applications are becoming increasingly data intensive, requiring both real-time and off-line manipulation of massive amounts of data. More and more programs and applications need to be run at the same time and huge and growing memory capacity is needed. Meanwhile, technology users continue to expect high (and even improved) speed and performance.

The fundamental performance and speed constraint on almost all computing systems is the memory system. The main memory, also known as the RAM (Random Access Memory), has a direct impact on how many programs can be executed at the same time and how much data is readily available to them. Limitations to effective memory can significantly hamper or even prevent the use of some advanced applications.

In the past, computer industry manufacturers have temporarily overcome processing speed limitations by reducing the circuit size, changing to parallel processor design as well as stacking memory chips in 3D. However, as transistor sizes approach the size of atoms, the physical limits of shrinking circuits are being reached and processors cannot be stacked without overheating. Manufacturing costs are becoming prohibitive, as the design and production process gets more complex.

Our innovation

Ziptilion™ is a patented compression/decompression technology that is capable of exploiting the low information entropy in computer memory to store and transport information as densely as possible, doubling memory capacity and bandwidth and potentially the speed and performance as well.

It can be installed in the System on Chips (SoC) of servers, smartphones, tablets, computers, including high-performance computers, and all sorts of connected (IoT) devices .

Doubling memory capacity and bandwidth leaves more space for software applications to utilize main memory, allowing data to be read faster by programs and for more programs to be executed at the same time, increasing the speed of the whole computer system.

Server manufacturers who integrate our technology will potentially realize impressive cost savings, up to 25% of total hardware costs. Furthermore, as a result of processing efficiencies, our solution will potentially halve current energy expenditure for DRAM memories.

The Solution

Ziptilion™ is an innovative data-compression technology that consists of a silicon memory IP block on a chip. It exploits the memory resources of computing devices more efficiently than any other solution existing in the market.

Ziptilion™’s potential is achieved by integrating accelerated compression and decompression on the data path between the processor and the main memory .

Figure 1 shows the problem. Here, the memory is full of data. It is shown with white data between the memory controller and main memory. The memory bus is saturated, so processing capacity goes unused. Physical memory must be added to increase memory capacity.

Figure 1

Figure 2 shows the solution : Our compression IP block is placed near the memory controller. Solution value:

  • More data can be stored in memory
  • More data can be transferred on the memory bus before saturation.
  • Increased computational performance, and/or
  • Reduces need for additional expensive physical memory.

Ziptilion™ manages the compressed memory by sampling and analysing data content and configuring compression and decompression accelerators for optimal results. It does this transparently to the system software , i.e. Ziptilion™ does not communicate with application software nor demand operating system changes so it can be installed in all computing systems , independently of the software they use.

Ziptilion™ is installed in the SoC in the same way as other existing IP blocks and different architectural integrations are possible. This allows software and external connections to work normally but the available memory capacity for applications and storage is increased two-fold.

Compression and decompression is data lossless, with ultra low latency, done in just a few nanoseconds.

Figure 2
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The Benefits of Ziptilion™

Increased capacity

Our compression algorithms and memory management approach typically offer a 2-3x memory expansion, depending on application and data.

Speed

In memory applications with for example DDR4 DRAM or faster memories, speed is not simply a nice benefit among others; If a compression scheme is not extremely fast then it can’t be used for memory applications regardless how nice the compression results are. Our IP block offers a scalable solution which can handle bandwidths of 20-40 GB/s per IP block or more.

A significant benefit of memory compression is the potential to reduce average memory access time since compressed memory data often will contain multiple cache lines when retrieved from memory.

Non-invasive to operating system and applications

The memory management software is designed to be compatible with common Linux distributions and to work transparently. Without need for modifications to operating system or applications.

Intelligent compression

The added memory benefits of increased capacity and bandwidth rely on steady and high compression performance of data memory. Memory (e.g., DRAM) data offers a fair amount of challenges. Since memory data changes character often depending on the set of currently used applications, it is important that the compression algorithms can dynamically monitor metadata and make intelligent and cost-benefit aware decisions on when the data in memory suffers from suboptimal compression and needs to be recompressed. It is also highly beneficial with algorithms intelligent enough to classify the data type currently being processed without added delay or latency, in order to pick the best performing compression scheme for a particular data type.

We combine proven statistical compression techniques with our own innovative patent protected ideas to make truly intelligent decision-making compression engines that work reliable and with high performance for the challenging working environment that memory data offers.

Up to 25% reduction of hardware cost

Server manufacturers who integrate our technology will potentially realize impressive cost savings, up to 25% of total hardware costs.

Up to 50% less energy consumption in servers

Furthermore, as a result of processing efficiencies, our solution will potentially halve current energy expenditure for DRAM memories. Typical DRAM memories have a power consumption of around 350-450 mW (milliwatts) per GB. For larger servers with 1 TB of memory this can require as much as 400 W per server. Due to our compression IP, a server user will be able to reduce the amount of physical memory capacity by up to 40-50%, reducing power consumption by as much as 160-200 W per server ( or 1,700 kWh per year).

Moreover, about 40% of the total energy in a datacenter is consumed in cooling the IT equipment so reducing server power will also proportionally reduce its cooling needs and thus the total energy consumption.

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