ZeroPoint provide a real time data compression technology that doubles memory capacity and bandwidth at radically higher power efficiency. The products are delivered as IP blocks that our customers integrate in their SoCs.
The computational density of integrated circuits is continuing to increase at a speed that is far from matched by the memory capacity and bandwidth. Our mission is to put unused resources to work. Our research shows that memory content is compressible (loss-less) with a factor of 2-3x. The benefit of our memory compression technology is up to 50% higher performance per watt of the system.
To accommodate the increasing demand for high performance, low latency security solutions, ZeroPoint has also developed an encryption/decryption IP core that can be provided stand alone or integrated with our compression IP.
SphinX AES-XTS Security IP
SphinX is designed to accommodate the speed, latency and throughput requirements of computer systems main memory. The IP implements the standard (NIST FIPS 197) AES cipher in XTS mode (IEEE Std 1619-2018). The SphinX family of cores covers a scalable IP with 128b and 256b key support, allowing the designer to choose the most efficient and effective core that satisfies the latency and throughput requirements.
The design is fully synchronous and supports independent, non-blocking encryption/decryption at main memory speed. SphinX is available for immediate licensing.
- High Performance and Low Latency industry standard encryption / decryption
- Independent non-blocking encryption and decryption channels
- 128b and 256b keys supported
- Supports AES-XTS mode, without Cipher Text Stealing (CTS)
- No additional memory required
- Key expansion included
- Fully pipelined design, optimized for high throughput and low latency
- Operating at main memory speed and throughput
- Modular and scalable architecture to easily accommodate customer data rates
SphinX is designed to accommodate the speed, latency and throughput requirements of high performance computer systems. This includes main memory and other high performance storage devices such as NvMe, SSD, Optane and PCIe connected devices. The IP implements the standard (NIST FIPS 197) AES cipher in XTS mode (IEEE Std 1619-2018). The IP is modular and can easily scale to higher throughput. The design is fully synchronous and supports independent, non-blocking encryption/decryption at main memory speed.
The IP support 128b and 256b keys and has an initialization mode and an operation mode. During the initialization mode the IP read the keys, expand them, and initiate the IP. The IP also support an optional bypass control.
- Main memory (DDR4/DDR5) independent, non-blocking encryption/decryption
- Hard drive (SATA, SAS, PCIe, NVMe and CXL) encryption/decryption compliant with the IEEE Std 1619-2018
- Applications that require integration of encryption/decryption into the data path
- Applications with high throughput, low latency and strong encryption requirements
- Applications requiring FIPS-197 certified encryption/decryption algorithms
IEEE Std 1619-2018, IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices https://standards.ieee.org/standard/1619-2018.html
NIST FIPS 197, Advanced Encryption Standard (AES) https://www.nist.gov/publications/advanced-encryption-standard-aes
Product marketing specification in development…