Our Technology

How we are different

Several solutions on the market improve storage capacity by various compression schemes and methods. ┬áSome solutions are even fast enough for memory capacity improvement. But no other solution has the combined benefits of ours: Speed In memory applications with for example DDR4 DRAM or faster memories, speed is not simply a nice benefit among others; If a compression scheme is not extremely fast then it can’t be used for memory applications regardless how nice the compression results are. Our compression algorithms are implemented in hardware logic instead of software, making them lightning fast. Intelligent compression The added Memory benefits of increased capacity and bandwidth rely on steady and high compression performance of data memory. Memory (e.g., DRAM) data offers a fair amount of challenges. Since memory data changes character often depending on the set of currently used applications, it is important that the compression algorithms can dynamically monitor metadata and make intelligent and cost-benefit aware decisions on when the data in memory suffers from suboptimal compression and needs to be recompressed. It is also highly beneficial with algorithms intelligent enough to classify the data type currently being processed without added delay or latency, in order to pick the best performing compression scheme for a particular data type. We combine proven statistical compression techniques with our own innovative patent protected ideas to make truly intelligent decision-making compression engines that work reliable and with high performance for the challenging working environment that memory data offers. Generality Intelligent, algorithms capable recompression and anticipation of data types offer great generality. We do well for many applications, spanning fields of Machine learning, Data Analytics, Graph analytics, CPU benchmark data, and financial derivatives. Our implementation on an FPGA accelerator board For FPGA accelerators, our technology is implemented as an IP block in connection with the memory controller.