ASIC/SOC implementation

How we are different Existing software based compression technologies such as ZRAM is today available to compress a fraction of the memory in order to reduce page swap out. Different to such solutions, our low-latency compression block can be used to compress the whole memory and does therefore offer significantly higher potential to expand memory. In addition to existing solutions, we also offer the option to physically extend the memory adress space which further reduces latency to access the expanded memory. Our solution compress and decompress on a cache line granularity to avoid compression/decompression overhead when handling memory access patterns without clear patterns. The approach is also compatible with page deduplication which can be handled synergistically by our IP block. Our approach is compatible with ECC and with memory encryption functionality when handled in the memory controller. Speed In memory applications with for example DDR4 DRAM or faster memories, speed is not simply a nice benefit among others; If a compression scheme is not extremely fast then it can’t be used for memory applications regardless how nice the compression results are. Our IP block offers a scalable solution which can handle bandwidths of 20-40 GB/s per IP block or more. Intelligent compression The added Memory benefits of increased capacity and bandwidth rely on steady and high compression performance of data memory. Memory (e.g., DRAM) data offers a fair amount of challenges. Since memory data changes character often depending on the set of currently used applications, it is important that the compression algorithms can dynamically monitor metadata and make intelligent and cost-benefit aware decisions on when the data in memory suffers from suboptimal compression and needs to be recompressed. It is also highly beneficial with algorithms intelligent enough to classify the data type currently being processed without added delay or latency, in order to pick the best performing compression scheme for a particular data type. We combine proven statistical compression techniques with our own innovative patent protected ideas to make truly intelligent decision-making compression engines that work reliable and with high performance for the challenging working environment that memory data offers.   Integration in SoC processor Our technology can either be integrated with the memory controller on the processor chip, or with the Last Level Cache (LLC) which also offers the possibility of cache compression.

FPGA implementation

Our technology has also been adapted to FPGAs and is offered as a soft IP block to increase bandwidth and/or capacity for increased performance of special purpose applications such as financial derivatives.