ZeroPoints technology put unused resources to work in high performance computer systems. The result is a system that achieve 50% higher power efficiency and system performance.
Our compression algorithms and memory management approach typically offer a 2-3x memory expansion, depending on application and data.
A significant benefit of memory compression is the potential to reduce average memory access time since compressed memory data often will contain multiple cache lines when retrieved from memory.
ZeroPoint also offers memory encryption, a technology that delivers high throughput and high security memory encryption, integrated with compression or stand alone.
ZeroPoint Technologies is offering Ziptilion™ a patented memory compression technology for high performance System on a Chip (SoC) processor subsystems. The technology effectively doubles the memory capacity and memory bandwidth. Our IP-block is placed on the memory access path and is transparent to the operating system and applications.
ZeroPoint also offers memory encryption, a technology that delivers high throughput and high security memory encryption, integrated with compression or stand alone.
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Our Ziptilion™ technology is a general compression and memory expansion solution that add value to all high-performance, memory challenging applications. The effect is increased system performance and/or reduced cost of components. It is also well documented that a system based on Ziptilion™ will have a better performance over power ratio. We recognize that these characteristics are found in most industry segments and products. Below are a few of the customer projects that ZeroPoint Technologies AB have engaged in with the Ziptilion™ technology.
Servers with extensive memory configurations that experience a working memory space and/or bandwidth challenge. Or an opportunity to offer significant DRAM cost reductions. Both opportunities are valid for the server-oriented product families when applying the Ziptilion™ technology.
Control and computation systems with well-defined data and where memory bandwidth and capacity are known bottlenecks. Cellular base station and infrastructure networking equipment are typical examples where Ziptilion™ technology has proven to add significant value.
ZeroPoint Technologies AB was incorporated in 2015 as a spinout from Chalmers University of Technology.
The Intellectual Property Portfolio related to computer memory management was then acquired from the founders and transferred into the new startup.
The technology and ideas behind ZeroPoint come from Professor Per Stenström’s research group, which is internationally recognized for research excellence within high-performance computing.
Since its creation, ZeroPoint has attracted skilled people from academia, industry, finance and the startup community and raised its first round of Venture Capital in 2016. The headquarter is in Göteborg, Sweden.
ZeroPoint Technologies AB has been appointed also this year: ONE OF THE HOTTEST STARTUPS IN SWEDEN 2020!
We have in our research made sure to evaluate our technology on a wide range of applications and sets of data. Based on industry use cases (see SPEC 2017) we typically see a compression ratio (CR%) of 50%, which means that the original memory footprint will only occupy 50% of the original space.
Based on this compression ratio there will obviously be significantly less data transferred from the DRAM controller to the DRAM memory. Depending on the application and nature of the data we have seen up to 50% less traffic over the DRAM interface due to the compression ratio (CR%) achieved.
The Ziptilion™ technology add significant value to any customer making their own ASIC or FPGA SoC (System on a Chip). A SoC is a System based on one or more CPUs, a memory subsystem and a set of accelerators and most likely proprietary logic blocks depending on the nature of the customer and application the SoC is targeting.
The Ziptilion™ technology is based on two parts, one HW IP block that is placed on the ASIC or FPGA silicon, and one Device driver SW that is put on the host CPU.
Depending on the application, architecture and technology the figures will be quite different. However, for reference we have made a comparison that we are happy to share. Just get in touch with the team with your inquiry.
The maximum throughput of the Ziptilion™ technology is depending on a combination of design, process node, cell libraries and bus architecture.
As an example we have an implementation of the Ziptilion™ technology today in a 28nm TSMC process, and the AXI bus is running at 800MHz, which result in a 32 GB/s throughput.
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