The Memory bottleneck problem

Several computer applications today face memory constrains, sometimes due to limited memory capacity (not enough memory), sometimes due to limited memory bandwidth (memory too slow). ZeroPoint Technologies uses novel compression approaches to develop and license a memory compression IP block placed on the SoC processor chip to effectively double memory capacity and memory bandwidth.

How we solve the problem

Different to standard available solutions like ZRAM, the low-latency IP block enables compression of the whole memory. The memory management software is designed to be compatible with common Linux versions and to work “under the hood” without required user interaction. ASIC performance data on performance, memory expansion, latency and traffic reduction is available and we are currently initiating several customer evaluation projects to validate performance and user value in various computer segments.

Increased capacity

Our compression algorithms and memory management approach typically offers a memory expansion of 2-3x depending on workload The expanded memory which is freed up from our IP compression block can either be accessed by the OS through our Linux compatible software driver, or directly by extending the physical adress space for maximum performance and low latency.

Increased effective memory bandwidth

A significant benefit of memory compression is the potential to reduce average memory access time since compressed memory data often will contain multiple cache lines when retrieved from memory. The net effect is the memory requests can often be cancelled as the requested cache line has already been fetched and cached in our IP block. The benefit is increased processing performance and lower average memory access times, which has been observed in benchmark suites such as SPEC2016.

Collaboration approach

ZeroPoint Technologies has developed several tools to quickly determine the the value potential for a particular system. By analyzing memory dumps and traces we get a first idea of the potential, and a good understanding of the potential which is further verified by sharing simulation models and cycle accurate code for further validation. We have several current and ongoing customer projects including Mobile applications and embedded systems, and are participating in a European consortium which is developing a high performance processor where we are responsible for delivering the memory subsystem.