Flash MX NVMe expansion

The Flash MX IP Core implements a hardware accelerator for zstd compression and decompression. Compute-intensive software-based compression is offloaded from the host to the IP, delivering high compression performance at unmatched power efficiency.

Overview

The Flash MX IP Core implements a hardware accelerator for zstd compression and decompression. Compute-intensive software-based compression is offloaded from the host to the IP, delivering high compression performance at unmatched power efficiency.

Standards

  • Hardware accelerated zstd

  • Compression algorithm: zstd

  • Interface: AXI4, CHI

Architecture

  • Modular architecture, enables scalability to meet customer throughput requirements

  • Architectural configuration parameters accessible to fine tune performance

HDL Source Licenses

  • Synthesizable System Verilog RTL (encrypted)

  • Implementation constraints

  • UVM testbench (self-checking)

  • Vectors for testbench and expected results

  • User Documentation

Features

  • Turn key solution: compression, compaction, memory management

  • Transparent addressing to operating system and applications

  • Operates on page granularity to enable high compression performance

Deliverables

  • Performance evaluation license

  • C++ compression model for integration in customer performance simulation model

FPGA evaluation license

  • Encrypted IP delivery (Xilinx)

Applications

Today costly host CPU cyscles are allocated to software based compression, when data is compressed before sent off over the interconnect to storage. The product benefit is more system performance at less power when the host is off-loaded with the software based compression, at the same time as the storage interconnect make up to 50% more bandwidth available and the storage device store 2-4x the amount of data.

Integration

Flash MX is integrated on the SoC as a hardware accelerator, a master node on the SoC interconnect. This could be either on the Host CPU or on the DPU / SmartNIC. Part of the integration includes a software driver.

Benefits

High performance and low latency hardware accelerated zstd at unmatched power efficiency. Off-loading CPU – More cycles to released to user work loads. Power efficiency – Less energy. Speed – Fast compression and low latency access. Compatible with AXI4/CHI, both 128-b and 256-b bus interface.

Performance / KPI

FeaturePerformance
Compression ratio:2-4x across diverse data sets
Compression throughput:(contact for details)
Decompression throughput:(contact for details)
Frequency:1.2GHz (@TSMC 5nm)
IP area:(Pending development details)

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SuperRAM

High performance and low latency hardware accelerated compression at unmatched power efficiency.

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Ziptilion™ BW

Delivers up to 25% more (LP)DDR bandwidth at nominal frequency and power, enabling a significantly more performance and energy efficient SoC.

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DenseMem

Double the CXL connected memory capacity with data DenseMem.

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Flash MX

Double the NvMe storage capacity with Flash MX.

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SphinX

High Performance and Low Latency industry-standard encryption / decryption. Independent non-blocking encryption and decryption channels.

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